1. Field of the Invention
The present application relates to cryptography operations. More specifically, the present application relates to methods and apparatus for improving data transfer efficiency in a cryptography accelerator system used to process network protocol data.
2. Description of Related Art
Conventional software and hardware designs for performing decryption and authentication operations are inefficient. Some techniques for performing authentication and encryption use a CPU extensively to perform cryptographic operations. When a device such as a network card receives data, a CPU performs decryption and authentication operations on the data after the data is passed from the network card to the CPU. Another technique for performing authentication and decryption entails having a host such as a CPU issue function calls to a cryptography accelerator to perform specific cryptographic operations. However, having a host transfer data to a cryptography accelerator and having a cryptography accelerator transfer data to a host entails even more read, write, load, and store type operations.
Having a large number of read, write, load, and store type system bus operations significantly hinders performance in cryptography accelerator systems. Furthermore, having multiple components also leads to data being read and reread multiple times.
Software, firmware and hardware techniques for performing decryption and authentication operations, such as DES, AES, RC4, MD5 and SHA1 operations used in secured sessions have been inefficient and resource intensive. Secured sessions, authentication operations, and decryption algorithms are described in Applied Cryptography, Bruce Schneier, John Wiley & Sons, Inc. (ISBN 0471128457), incorporated by reference in its entirety for all purposes.
It is therefore desirable to provide methods and apparatus for improving decryption and authentication processing with respect to some or all of the performance limitations noted above.